1. Field of the Invention
The present invention relates generally to the design of semiconductor integrated circuits (“ICs”) and more specifically, to using redundantly tied metal fill for voltage drop (as a function of current and resistance, also referred to as “IR-drop”) and layout density optimization.
2. Background of the Invention
Semiconductor integrated circuits (ICs) are typically composed of layer structures consisting of several layers of conducting, insulating and other materials. These materials are structured in the horizontal dimension by fabrication processes that transfer patterns defined in physical designs or layouts. Further, IC design processes typically employ various rules to ensure uniform density requirements and signal integrity requirements.
The multilayer interconnect in ICs allow various transistors to be connected to complete a circuit. In the metal layers of an IC chip, there are some areas with high interconnect density and others with low density. Certain fabrication processing steps, such as the chemical mechanical polishing (“CMP”) process used for planarizing interlayer dielectrics, have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameter. Traditional methods to achieve uniformity include insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Uniformity of CMP depends on uniformity of features on the interconnect layer beneath a given dielectric layer to avoid dishing and other irregularities. Metal-fill patterning is the process of filling the large open areas on each metal layer with a metal pattern, which is either grounded or left floating, to compensate for pattern-driven variation. A metal fill can be floating or tied. A tied metal fill is connected to ground or power. A floating metal fill is not connected to a ground or power and is electrically floating. A problem with floating metal fill geometries is that their capacitive values are unknown and they will capacitively couple with the signal lines above and below.
Another challenge in IC design involves failures caused by signal integrity problems. IR drop is one such signal integrity effects caused by wire resistance and current drawn from the power and ground grids. If the wire resistance is too great or the cell current is higher than predicted, an unacceptable voltage drop may occur. The voltage drop causes the voltage supplied to the affected cells to be lower than required, leading to larger gate and signal delays, which in turn can cause timing degradation in the signal paths as well as clock skew. In the worst case, the voltage drop may be large enough that transistors fail to switch correctly, causing the chip to fail.
In most conventional IC design flows, signal integrity analysis is performed as a post-layout activity. Attempting to analyze and correct for these issues post-layout often results in costly and time-consuming design iterations, failed schedules, reduced product performance and even larger die sizes with poorer manufacturing yield.
It is therefore desirable to improve on existing methods to address signal integrity and metal-fill issues as an integral part of the design flow.